Showing results for "IEEE Electron Device Letters" 1-14 of 14

The publications on this page are generated nightly from the NCSU Library's Scholarly Publications Repository. This repository is by no means a fully comprehensive listing of publications. Publications can be added to the repository manually by visiting the Publications Repository Submission Form.

Title Journal Year
Thermal properties of AlGaN/GaN HFETs on bulk GaN substrates IEEE Electron Device Letters, 33(3), 366-368. Killat, N., Montes, M., Pomeroy, J. W., Paskova, T., Evans, K. R., Leach, J., Li, X., Ozgur, U., Morkoc, H., Chabak, K. D., Crespo, A., Gillespie, J. K., Fitch, R., Kossler, M., Walker, D. E., Trejo, M., Via, G. D., Blevins, J. D., & Kuball, M. 2012
Active-matrix microelectrode arrays integrated with vertically aligned carbon nanofibers IEEE Electron Device Letters, 30(3), 254-257. Park, J., Kwon, S., Jun, S. I., Mcknight, T. E., Melechko, A. V., Simpson, M. L., Dhindsa, M., Heikenfeld, J., & Rack, P. D. 2009
High performance 0.14 mu m gate-length AlGaN/GaN power HEMTs on SiC IEEE Electron Device Letters, 24(11), 677-679. Jessen, G. H., Fitch, R. C., Gillespie, J. K., Via, G. D., Moser, N. A., Yannuzzi, M. J., Crespo, A., Sewell, J. S., Dettmer, R. W., Jenkins, T. J., Davis, R. F., Yang, J., Khan, M. A., & Binari, S. C. 2003
Effect of the composition on the electrical properties of TaSixNy metal gate electrodes IEEE Electron Device Letters, 24(7), 439-441. Suh, Y. S., Heuss, G. P., Lee, J. H., & Misra, V. 2003
The effects of interfacial sub-oxide transition regions and monolayer level nitridation on tunneling currents in silicon devices IEEE Electron Device Letters, 21(2), 76-78. Yang, H., Niimi, H., Keister, J. W., & Lucovsky, G. 2000
1.6 nm oxide equivalent gate dielectrics using nitride/oxide (N/O) composites prepared by RPECVD/oxidation process IEEE Electron Device Letters, 21(3), 116-118. Wu, Y. D., Lee, Y. M., & Lucovsky, G. 2000
Electrical properties of RuO2 gate electrodes for dual metal gate Si-CMOS IEEE Electron Device Letters, 21(12), 593-595. Zhong, H. C., Heuss, G., & Misra, V. 2000
Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides IEEE Electron Device Letters, 20(6), 262-264. Wu, Y. D., Xiang, Q., Bang, D., Lucovsky, G., & Lin, M. R. 1999
Analysis of capacitor breakdown mechanisms due to crystal- originated pits IEEE Electron Device Letters, 20(10), 504-506. Ono, T., Rozgonyi, G., Horie, H., Miyazaki, M., & Tsuya, H. 1999
Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors IEEE Electron Device Letters, 20(4), 179-181. Henson, W. K., Ahmed, K. Z., Vogel, E. M., Hauser, J. R., Wortman, J. J., Venables, R. D., Xu, M., & Venables, D. 1999
Ultrathin oxide-nitride gate dielectric MOSFET's IEEE Electron Device Letters, 19(4), 106-108. Parker, C. G., Lucovsky, G., & Hauser, J. R. 1998
Ultrathin nitride/oxide (N/O) gate dielectrics for p(+)-polysilicon gated PMOSFET's prepared by a combined remote plasma enhanced CVD thermal oxidation process IEEE Electron Device Letters, 19(10), 367-369. Wu, Y. D., & Lucovsky, G. 1998
Self-aligned gate and source drain contacts in inverted-staggered a-Si:H thin-film transistors fabricated using selective area silicon PECVD IEEE Electron Device Letters, 19(6), 180-182. Yang, C. S., Read, W. W., Arthur, C., Srinivasan, E., & Parsons, G. N. 1998
Enhanced mobility top-gate amorphous silicon thin film transistor using selectively deposited source/drain contacts IEEE Electron Device Letters, 3, 80-83. Parsons, G.N. 1992

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